================================================================ == Synthesis Summary Report of 'matv_mult_opt' ================================================================ + General Information: * Date: Fri Dec 1 20:21:26 2023 * Version: 2023.1 (Build 3854077 on May 4 2023) * Project: proj * Solution: solution (Vivado IP Flow Target) * Product family: virtexuplus * Target device: xcu250-figd2104-2L-e + Performance & Resource Estimates: PS: '+' for module; 'o' for loop; '*' for dataflow +---------------------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+------------+------------+---------+ | Modules | Issue| | Latency | Latency | Iteration| | Trip | | | | | | | | & Loops | Type | Slack| (cycles)| (ns) | Latency | Interval| Count| Pipelined| BRAM | DSP | FF | LUT | URAM | +---------------------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+------------+------------+---------+ |+ matv_mult_opt | -| 0.00| 4476| 4.476e+04| -| 4477| -| no| 4 (~0%)| 48 (~0%)| 4434 (~0%)| 6157 (~0%)| 15 (1%)| | + matv_mult_opt_Pipeline_I_load_a_J_load_a | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 65 (~0%)| 186 (~0%)| -| | o I_load_a_J_load_a | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_load_b | -| 0.00| 67| 670.000| -| 67| -| no| -| -| 59 (~0%)| 80 (~0%)| -| | o I_load_b | -| 7.30| 65| 650.000| 3| 1| 64| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_loop | -| 0.14| 259| 2.590e+03| -| 259| -| no| -| 48 (~0%)| 291 (~0%)| 2925 (~0%)| -| | o I_loop | II| 7.30| 257| 2.570e+03| 6| 4| 64| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_store_c | -| 0.00| 67| 670.000| -| 67| -| no| -| -| 45 (~0%)| 78 (~0%)| -| | o I_store_c | -| 7.30| 65| 650.000| 3| 1| 64| yes| -| -| -| -| -| +---------------------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+------------+------------+---------+ ================================================================ == HW Interfaces ================================================================ * M_AXI +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | Interface | Data Width | Address Width | Latency | Offset | Register | Max Widen | Max Read | Max Write | Num Read | Num Write | Resource Estimate | | | (SW->HW) | | | | | Bitwidth | Burst Length | Burst Length | Outstanding | Outstanding | | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | m_axi_aximm1 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 16 | 16 | 16 | BRAM=2 | | m_axi_aximm2 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 1 | 16 | 16 | BRAM=2 | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ * S_AXILITE Interfaces +---------------+------------+---------------+--------+----------+ | Interface | Data Width | Address Width | Offset | Register | +---------------+------------+---------------+--------+----------+ | s_axi_control | 32 | 6 | 16 | 0 | +---------------+------------+---------------+--------+----------+ * S_AXILITE Registers +---------------+----------+--------+-------+--------+------------------+ | Interface | Register | Offset | Width | Access | Description | +---------------+----------+--------+-------+--------+------------------+ | s_axi_control | c_1 | 0x10 | 32 | W | Data signal of c | | s_axi_control | c_2 | 0x14 | 32 | W | Data signal of c | | s_axi_control | a_1 | 0x1c | 32 | W | Data signal of a | | s_axi_control | a_2 | 0x20 | 32 | W | Data signal of a | | s_axi_control | b_1 | 0x28 | 32 | W | Data signal of b | | s_axi_control | b_2 | 0x2c | 32 | W | Data signal of b | +---------------+----------+--------+-------+--------+------------------+ * TOP LEVEL CONTROL +-----------+------------+-----------------------------------+ | Interface | Type | Ports | +-----------+------------+-----------------------------------+ | ap_clk | clock | ap_clk | | ap_rst_n | reset | ap_rst_n | | ap_ctrl | ap_ctrl_hs | ap_done ap_idle ap_ready ap_start | +-----------+------------+-----------------------------------+ ================================================================ == SW I/O Information ================================================================ * Top Function Arguments +----------+-----------+-------------+ | Argument | Direction | Datatype | +----------+-----------+-------------+ | c | inout | int* | | a | inout | int const * | | b | in | int const * | +----------+-----------+-------------+ * SW-to-HW Mapping +----------+---------------+-----------+----------+-------------------------------+ | Argument | HW Interface | HW Type | HW Usage | HW Info | +----------+---------------+-----------+----------+-------------------------------+ | c | m_axi_aximm1 | interface | | | | c | s_axi_control | register | offset | name=c_1 offset=0x10 range=32 | | c | s_axi_control | register | offset | name=c_2 offset=0x14 range=32 | | a | m_axi_aximm1 | interface | | | | a | s_axi_control | register | offset | name=a_1 offset=0x1c range=32 | | a | s_axi_control | register | offset | name=a_2 offset=0x20 range=32 | | b | m_axi_aximm2 | interface | | | | b | s_axi_control | register | offset | name=b_1 offset=0x28 range=32 | | b | s_axi_control | register | offset | name=b_2 offset=0x2c range=32 | +----------+---------------+-----------+----------+-------------------------------+ ================================================================ == M_AXI Burst Information ================================================================ Note: All burst requests might be further partitioned into multiple requests during RTL generation based on max_read_burst_length or max_write_burst_length settings. * Inferred Burst Summary +--------------+-----------+--------+-------+-----------+-------------------------------+ | HW Interface | Direction | Length | Width | Loop | Loop Location | +--------------+-----------+--------+-------+-----------+-------------------------------+ | m_axi_aximm1 | read | 4096 | 32 | I_load_a | ../src/matv_mult_opt.cpp:27:9 | | m_axi_aximm1 | write | 64 | 32 | I_store_c | ../src/matv_mult_opt.cpp:88:9 | | m_axi_aximm2 | read | 64 | 32 | I_load_b | ../src/matv_mult_opt.cpp:40:9 | +--------------+-----------+--------+-------+-----------+-------------------------------+ * All M_AXI Variable Accesses +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | HW Interface | Variable | Access Location | Direction | Burst Status | Length | Loop | Loop Location | Resolution | Problem | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:34:18 | read | Widen Fail | | J_load_a | ../src/matv_mult_opt.cpp:32:13 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:34:18 | read | Inferred | 4096 | I_load_a | ../src/matv_mult_opt.cpp:27:9 | | | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:90:11 | write | Widen Fail | | I_store_c | ../src/matv_mult_opt.cpp:88:9 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:90:11 | write | Inferred | 64 | I_store_c | ../src/matv_mult_opt.cpp:88:9 | | | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:42:15 | read | Widen Fail | | I_load_b | ../src/matv_mult_opt.cpp:40:9 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:42:15 | read | Inferred | 64 | I_load_b | ../src/matv_mult_opt.cpp:40:9 | | | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ * Resolution URL: www.xilinx.com/cgi-bin/docs/rdoc?v=2023.1;t=hls+guidance;d=XXX-YYY.html (replace XXX-YYY with column value) ================================================================ == Bind Op Report ================================================================ +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ | Name | DSP | Pragma | Variable | Op | Impl | Latency | +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ | + matv_mult_opt | 48 | | | | | | | + matv_mult_opt_Pipeline_I_load_a_J_load_a | 0 | | | | | | | add_ln27_1_fu_126_p2 | - | | add_ln27_1 | add | fabric | 0 | | add_ln27_fu_149_p2 | - | | add_ln27 | add | fabric | 0 | | add_ln34_fu_193_p2 | - | | add_ln34 | add | fabric | 0 | | add_ln32_fu_204_p2 | - | | add_ln32 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_load_b | 0 | | | | | | | add_ln40_fu_96_p2 | - | | add_ln40 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_loop | 48 | | | | | | | add_ln49_fu_1462_p2 | - | | add_ln49 | add | fabric | 0 | | mul_32s_32s_32_1_1_U7 | 3 | | mul_ln55 | mul | auto | 0 | | mul_32s_32s_32_1_1_U8 | 3 | | mul_ln55_1 | mul | auto | 0 | | mul_32s_32s_32_1_1_U9 | 3 | | mul_ln55_2 | mul | auto | 0 | | mul_32s_32s_32_1_1_U10 | 3 | | mul_ln55_3 | mul | auto | 0 | | mul_32s_32s_32_1_1_U11 | 3 | | mul_ln55_4 | mul | auto | 0 | | mul_32s_32s_32_1_1_U12 | 3 | | mul_ln55_5 | mul | auto | 0 | | mul_32s_32s_32_1_1_U13 | 3 | | mul_ln55_6 | mul | auto | 0 | | mul_32s_32s_32_1_1_U14 | 3 | | mul_ln55_7 | mul | auto | 0 | | mul_32s_32s_32_1_1_U15 | 3 | | mul_ln55_8 | mul | auto | 0 | | mul_32s_32s_32_1_1_U16 | 3 | | mul_ln55_9 | mul | auto | 0 | | mul_32s_32s_32_1_1_U17 | 3 | | mul_ln55_10 | mul | auto | 0 | | mul_32s_32s_32_1_1_U18 | 3 | | mul_ln55_11 | mul | auto | 0 | | mul_32s_32s_32_1_1_U19 | 3 | | mul_ln55_12 | mul | auto | 0 | | mul_32s_32s_32_1_1_U20 | 3 | | mul_ln55_13 | mul | auto | 0 | | mul_32s_32s_32_1_1_U21 | 3 | | mul_ln55_14 | mul | auto | 0 | | mul_32s_32s_32_1_1_U22 | 3 | | mul_ln55_15 | mul | auto | 0 | | mul_32s_32s_32_1_1_U7 | 3 | | mul_ln55_16 | mul | auto | 0 | | mul_32s_32s_32_1_1_U8 | 3 | | mul_ln55_17 | mul | auto | 0 | | mul_32s_32s_32_1_1_U9 | 3 | | mul_ln55_18 | mul | auto | 0 | | mul_32s_32s_32_1_1_U10 | 3 | | mul_ln55_19 | mul | auto | 0 | | mul_32s_32s_32_1_1_U11 | 3 | | mul_ln55_20 | mul | auto | 0 | | mul_32s_32s_32_1_1_U12 | 3 | | mul_ln55_21 | mul | auto | 0 | | mul_32s_32s_32_1_1_U13 | 3 | | mul_ln55_22 | mul | auto | 0 | | mul_32s_32s_32_1_1_U14 | 3 | | mul_ln55_23 | mul | auto | 0 | | mul_32s_32s_32_1_1_U15 | 3 | | mul_ln55_24 | mul | auto | 0 | | mul_32s_32s_32_1_1_U16 | 3 | | mul_ln55_25 | mul | auto | 0 | | mul_32s_32s_32_1_1_U17 | 3 | | mul_ln55_26 | mul | auto | 0 | | mul_32s_32s_32_1_1_U18 | 3 | | mul_ln55_27 | mul | auto | 0 | | mul_32s_32s_32_1_1_U19 | 3 | | mul_ln55_28 | mul | auto | 0 | | mul_32s_32s_32_1_1_U20 | 3 | | mul_ln55_29 | mul | auto | 0 | | mul_32s_32s_32_1_1_U21 | 3 | | mul_ln55_30 | mul | auto | 0 | | mul_32s_32s_32_1_1_U22 | 3 | | mul_ln55_31 | mul | auto | 0 | | mul_32s_32s_32_1_1_U7 | 3 | | mul_ln55_32 | mul | auto | 0 | | mul_32s_32s_32_1_1_U8 | 3 | | mul_ln55_33 | mul | auto | 0 | | mul_32s_32s_32_1_1_U9 | 3 | | mul_ln55_34 | mul | auto | 0 | | mul_32s_32s_32_1_1_U10 | 3 | | mul_ln55_35 | mul | auto | 0 | | mul_32s_32s_32_1_1_U11 | 3 | | mul_ln55_36 | mul | auto | 0 | | mul_32s_32s_32_1_1_U12 | 3 | | mul_ln55_37 | mul | auto | 0 | | mul_32s_32s_32_1_1_U13 | 3 | | mul_ln55_38 | mul | auto | 0 | | mul_32s_32s_32_1_1_U14 | 3 | | mul_ln55_39 | mul | auto | 0 | | mul_32s_32s_32_1_1_U15 | 3 | | mul_ln55_40 | mul | auto | 0 | | mul_32s_32s_32_1_1_U16 | 3 | | mul_ln55_41 | mul | auto | 0 | | mul_32s_32s_32_1_1_U17 | 3 | | mul_ln55_42 | mul | auto | 0 | | mul_32s_32s_32_1_1_U18 | 3 | | mul_ln55_43 | mul | auto | 0 | | mul_32s_32s_32_1_1_U19 | 3 | | mul_ln55_44 | mul | auto | 0 | | mul_32s_32s_32_1_1_U20 | 3 | | mul_ln55_45 | mul | auto | 0 | | mul_32s_32s_32_1_1_U21 | 3 | | mul_ln55_46 | mul | auto | 0 | | mul_32s_32s_32_1_1_U22 | 3 | | mul_ln55_47 | mul | auto | 0 | | mul_32s_32s_32_1_1_U7 | 3 | | mul_ln55_48 | mul | auto | 0 | | mul_32s_32s_32_1_1_U8 | 3 | | mul_ln55_49 | mul | auto | 0 | | mul_32s_32s_32_1_1_U9 | 3 | | mul_ln55_50 | mul | auto | 0 | | mul_32s_32s_32_1_1_U10 | 3 | | mul_ln55_51 | mul | auto | 0 | | mul_32s_32s_32_1_1_U11 | 3 | | mul_ln55_52 | mul | auto | 0 | | mul_32s_32s_32_1_1_U12 | 3 | | mul_ln55_53 | mul | auto | 0 | | mul_32s_32s_32_1_1_U13 | 3 | | mul_ln55_54 | mul | auto | 0 | | mul_32s_32s_32_1_1_U14 | 3 | | mul_ln55_55 | mul | auto | 0 | | mul_32s_32s_32_1_1_U15 | 3 | | mul_ln55_56 | mul | auto | 0 | | mul_32s_32s_32_1_1_U16 | 3 | | mul_ln55_57 | mul | auto | 0 | | mul_32s_32s_32_1_1_U17 | 3 | | mul_ln55_58 | mul | auto | 0 | | mul_32s_32s_32_1_1_U18 | 3 | | mul_ln55_59 | mul | auto | 0 | | mul_32s_32s_32_1_1_U19 | 3 | | mul_ln55_60 | mul | auto | 0 | | mul_32s_32s_32_1_1_U20 | 3 | | mul_ln55_61 | mul | auto | 0 | | mul_32s_32s_32_1_1_U21 | 3 | | mul_ln55_62 | mul | auto | 0 | | mul_32s_32s_32_1_1_U22 | 3 | | mul_ln55_63 | mul | auto | 0 | | grp_fu_1348_p2 | - | | add_ln55_1 | add | fabric | 0 | | grp_fu_1360_p2 | - | | add_ln55_4 | add | fabric | 0 | | grp_fu_1372_p2 | - | | add_ln55_7 | add | fabric | 0 | | grp_fu_1378_p2 | - | | add_ln55_8 | add | fabric | 0 | | grp_fu_1396_p2 | - | | add_ln55_11 | add | fabric | 0 | | grp_fu_1348_p2 | - | | add_ln55_16 | add | fabric | 0 | | grp_fu_1360_p2 | - | | add_ln55_19 | add | fabric | 0 | | grp_fu_1372_p2 | - | | add_ln55_22 | add | fabric | 0 | | grp_fu_1378_p2 | - | | add_ln55_23 | add | fabric | 0 | | grp_fu_1396_p2 | - | | add_ln55_26 | add | fabric | 0 | | add_ln55_31_fu_2160_p2 | - | | add_ln55_31 | add | fabric | 0 | | grp_fu_1348_p2 | - | | add_ln55_32 | add | fabric | 0 | | grp_fu_1360_p2 | - | | add_ln55_35 | add | fabric | 0 | | grp_fu_1372_p2 | - | | add_ln55_38 | add | fabric | 0 | | grp_fu_1378_p2 | - | | add_ln55_39 | add | fabric | 0 | | grp_fu_1396_p2 | - | | add_ln55_42 | add | fabric | 0 | | grp_fu_1348_p2 | - | | add_ln55_47 | add | fabric | 0 | | grp_fu_1360_p2 | - | | add_ln55_50 | add | fabric | 0 | | grp_fu_1372_p2 | - | | add_ln55_53 | add | fabric | 0 | | grp_fu_1378_p2 | - | | add_ln55_54 | add | fabric | 0 | | grp_fu_1396_p2 | - | | add_ln55_57 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_store_c | 0 | | | | | | | add_ln88_fu_101_p2 | - | | add_ln88 | add | fabric | 0 | +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ ================================================================ == Bind Storage Report ================================================================ +-----------------+------+------+--------+----------+---------+------+---------+ | Name | BRAM | URAM | Pragma | Variable | Storage | Impl | Latency | +-----------------+------+------+--------+----------+---------+------+---------+ | + matv_mult_opt | 4 | 15 | | | | | | | a_local_U | - | 1 | | a_local | rom_np | auto | 1 | | b_local_U | - | - | | b_local | ram_s2p | auto | 1 | | c_local_U | - | - | | c_local | ram_1p | auto | 1 | +-----------------+------+------+--------+----------+---------+------+---------+ ================================================================ == Pragma Report ================================================================ * Valid Pragma Syntax +----------------+-----------------------------------------------------------------------------------+-------------------------------------------------+ | Type | Options | Location | +----------------+-----------------------------------------------------------------------------------+-------------------------------------------------+ | interface | m_axi port=a bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:10 in matv_mult_opt, a | | interface | m_axi port=b bundle=aximm2 max_read_burst_length = 16 max_write_burst_length = 1 | ../src/matv_mult_opt.cpp:11 in matv_mult_opt, b | | interface | m_axi port=c bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:12 in matv_mult_opt, c | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:30 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:33 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:41 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:50 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:54 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:89 in matv_mult_opt | +----------------+-----------------------------------------------------------------------------------+-------------------------------------------------+