================================================================ == Synthesis Summary Report of 'matv_mult_opt' ================================================================ + General Information: * Date: Sat Dec 2 18:10:44 2023 * Version: 2023.1 (Build 3854077 on May 4 2023) * Project: proj * Solution: solution (Vivado IP Flow Target) * Product family: virtexuplus * Target device: xcu250-figd2104-2L-e + Performance & Resource Estimates: PS: '+' for module; 'o' for loop; '*' for dataflow +------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+-------------+-----+ | Modules | Issue| | Latency | Latency | Iteration| | Trip | | | | | | | | & Loops | Type | Slack| (cycles)| (ns) | Latency | Interval| Count| Pipelined| BRAM | DSP | FF | LUT | URAM| +------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+-------------+-----+ |+ matv_mult_opt* | -| 0.00| 4283| 4.283e+04| -| 4108| -| dataflow| 4 (~0%)| 192 (1%)| 19621 (~0%)| 14785 (~0%)| -| | + entry_proc | -| 5.89| 0| 0.000| -| 0| -| no| -| -| 2 (~0%)| 20 (~0%)| -| | + load_matA | -| 0.00| 4107| 4.107e+04| -| 4107| -| no| -| -| 213 (~0%)| 193 (~0%)| -| | o I_load_a_J_load_a | -| 7.30| 4105| 4.105e+04| 11| 1| 4096| yes| -| -| -| -| -| | + load_vecB | -| 0.00| 74| 740.000| -| 74| -| no| -| -| 4322 (~0%)| 1309 (~0%)| -| | o I_load_b | -| 7.30| 72| 720.000| 10| 1| 64| yes| -| -| -| -| -| | + mat_mult | -| 0.31| 101| 1.010e+03| -| 101| -| no| -| 192 (1%)| 4310 (~0%)| 4004 (~0%)| -| | + mat_mult_Pipeline_I_loop | -| 0.36| 66| 660.000| -| 66| -| no| -| 192 (1%)| 2256 (~0%)| 3510 (~0%)| -| | o I_loop | -| 7.30| 64| 640.000| 2| 1| 64| yes| -| -| -| -| -| | + store_result | -| 0.00| 73| 730.000| -| 73| -| no| -| -| 250 (~0%)| 469 (~0%)| -| | o I_store_c | -| 7.30| 71| 710.000| 9| 1| 64| yes| -| -| -| -| -| +------------------------------+------+------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+-------------+-----+ ================================================================ == HW Interfaces ================================================================ * M_AXI +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | Interface | Data Width | Address Width | Latency | Offset | Register | Max Widen | Max Read | Max Write | Num Read | Num Write | Resource Estimate | | | (SW->HW) | | | | | Bitwidth | Burst Length | Burst Length | Outstanding | Outstanding | | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | m_axi_aximm1 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 16 | 16 | 16 | BRAM=2 | | m_axi_aximm2 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 1 | 16 | 16 | BRAM=2 | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ * S_AXILITE Interfaces +---------------+------------+---------------+--------+----------+ | Interface | Data Width | Address Width | Offset | Register | +---------------+------------+---------------+--------+----------+ | s_axi_control | 32 | 6 | 16 | 0 | +---------------+------------+---------------+--------+----------+ * S_AXILITE Registers +---------------+----------+--------+-------+--------+------------------+ | Interface | Register | Offset | Width | Access | Description | +---------------+----------+--------+-------+--------+------------------+ | s_axi_control | c_1 | 0x10 | 32 | W | Data signal of c | | s_axi_control | c_2 | 0x14 | 32 | W | Data signal of c | | s_axi_control | a_1 | 0x1c | 32 | W | Data signal of a | | s_axi_control | a_2 | 0x20 | 32 | W | Data signal of a | | s_axi_control | b_1 | 0x28 | 32 | W | Data signal of b | | s_axi_control | b_2 | 0x2c | 32 | W | Data signal of b | +---------------+----------+--------+-------+--------+------------------+ * TOP LEVEL CONTROL +-----------+------------+-----------------------------------+ | Interface | Type | Ports | +-----------+------------+-----------------------------------+ | ap_clk | clock | ap_clk | | ap_rst_n | reset | ap_rst_n | | ap_ctrl | ap_ctrl_hs | ap_done ap_idle ap_ready ap_start | +-----------+------------+-----------------------------------+ ================================================================ == SW I/O Information ================================================================ * Top Function Arguments +----------+-----------+-------------+ | Argument | Direction | Datatype | +----------+-----------+-------------+ | c | inout | int* | | a | inout | int const * | | b | in | int const * | +----------+-----------+-------------+ * SW-to-HW Mapping +----------+---------------+-----------+----------+-------------------------------+ | Argument | HW Interface | HW Type | HW Usage | HW Info | +----------+---------------+-----------+----------+-------------------------------+ | c | m_axi_aximm1 | interface | | | | c | s_axi_control | register | offset | name=c_1 offset=0x10 range=32 | | c | s_axi_control | register | offset | name=c_2 offset=0x14 range=32 | | a | m_axi_aximm1 | interface | | | | a | s_axi_control | register | offset | name=a_1 offset=0x1c range=32 | | a | s_axi_control | register | offset | name=a_2 offset=0x20 range=32 | | b | m_axi_aximm2 | interface | | | | b | s_axi_control | register | offset | name=b_1 offset=0x28 range=32 | | b | s_axi_control | register | offset | name=b_2 offset=0x2c range=32 | +----------+---------------+-----------+----------+-------------------------------+ ================================================================ == M_AXI Burst Information ================================================================ Note: All burst requests might be further partitioned into multiple requests during RTL generation based on max_read_burst_length or max_write_burst_length settings. * Inferred Burst Summary +--------------+-----------+--------+-------+-----------+-------------------------------+ | HW Interface | Direction | Length | Width | Loop | Loop Location | +--------------+-----------+--------+-------+-----------+-------------------------------+ | m_axi_aximm1 | read | 4096 | 32 | I_load_a | ../src/matv_mult_opt.cpp:8:5 | | m_axi_aximm1 | write | 64 | 32 | I_store_c | ../src/matv_mult_opt.cpp:49:5 | | m_axi_aximm2 | read | 64 | 32 | I_load_b | ../src/matv_mult_opt.cpp:24:5 | +--------------+-----------+--------+-------+-----------+-------------------------------+ * All M_AXI Variable Accesses +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+-------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | HW Interface | Variable | Access Location | Direction | Burst Status | Length | Loop | Loop Location | Resolution | Problem | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+-------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:15:30 | read | Widen Fail | | J_load_a | ../src/matv_mult_opt.cpp:13:9 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:15:30 | read | Inferred | 4096 | I_load_a | ../src/matv_mult_opt.cpp:8:5 | | | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:51:11 | write | Widen Fail | | I_store_c | ../src/matv_mult_opt.cpp:49:5 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:51:11 | write | Inferred | 64 | I_store_c | ../src/matv_mult_opt.cpp:49:5 | | | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:26:15 | read | Widen Fail | | I_load_b | ../src/matv_mult_opt.cpp:24:5 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:26:15 | read | Inferred | 64 | I_load_b | ../src/matv_mult_opt.cpp:24:5 | | | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+-------------------------------+------------+-------------------------------------------------------------------------------------------------------+ * Resolution URL: www.xilinx.com/cgi-bin/docs/rdoc?v=2023.1;t=hls+guidance;d=XXX-YYY.html (replace XXX-YYY with column value) ================================================================ == Bind Op Report ================================================================ +------------------------------+-----+--------+-------------+------+--------+---------+ | Name | DSP | Pragma | Variable | Op | Impl | Latency | +------------------------------+-----+--------+-------------+------+--------+---------+ | + matv_mult_opt | 192 | | | | | | | b_local_U | - | | b_local | fifo | srl | 0 | | b_local_1_U | - | | b_local_1 | fifo | srl | 0 | | b_local_2_U | - | | b_local_2 | fifo | srl | 0 | | b_local_3_U | - | | b_local_3 | fifo | srl | 0 | | b_local_4_U | - | | b_local_4 | fifo | srl | 0 | | b_local_5_U | - | | b_local_5 | fifo | srl | 0 | | b_local_6_U | - | | b_local_6 | fifo | srl | 0 | | b_local_7_U | - | | b_local_7 | fifo | srl | 0 | | b_local_8_U | - | | b_local_8 | fifo | srl | 0 | | b_local_9_U | - | | b_local_9 | fifo | srl | 0 | | b_local_10_U | - | | b_local_10 | fifo | srl | 0 | | b_local_11_U | - | | b_local_11 | fifo | srl | 0 | | b_local_12_U | - | | b_local_12 | fifo | srl | 0 | | b_local_13_U | - | | b_local_13 | fifo | srl | 0 | | b_local_14_U | - | | b_local_14 | fifo | srl | 0 | | b_local_15_U | - | | b_local_15 | fifo | srl | 0 | | b_local_16_U | - | | b_local_16 | fifo | srl | 0 | | b_local_17_U | - | | b_local_17 | fifo | srl | 0 | | b_local_18_U | - | | b_local_18 | fifo | srl | 0 | | b_local_19_U | - | | b_local_19 | fifo | srl | 0 | | b_local_20_U | - | | b_local_20 | fifo | srl | 0 | | b_local_21_U | - | | b_local_21 | fifo | srl | 0 | | b_local_22_U | - | | b_local_22 | fifo | srl | 0 | | b_local_23_U | - | | b_local_23 | fifo | srl | 0 | | b_local_24_U | - | | b_local_24 | fifo | srl | 0 | | b_local_25_U | - | | b_local_25 | fifo | srl | 0 | | b_local_26_U | - | | b_local_26 | fifo | srl | 0 | | b_local_27_U | - | | b_local_27 | fifo | srl | 0 | | b_local_28_U | - | | b_local_28 | fifo | srl | 0 | | b_local_29_U | - | | b_local_29 | fifo | srl | 0 | | b_local_30_U | - | | b_local_30 | fifo | srl | 0 | | b_local_31_U | - | | b_local_31 | fifo | srl | 0 | | b_local_32_U | - | | b_local_32 | fifo | srl | 0 | | b_local_33_U | - | | b_local_33 | fifo | srl | 0 | | b_local_34_U | - | | b_local_34 | fifo | srl | 0 | | b_local_35_U | - | | b_local_35 | fifo | srl | 0 | | b_local_36_U | - | | b_local_36 | fifo | srl | 0 | | b_local_37_U | - | | b_local_37 | fifo | srl | 0 | | b_local_38_U | - | | b_local_38 | fifo | srl | 0 | | b_local_39_U | - | | b_local_39 | fifo | srl | 0 | | b_local_40_U | - | | b_local_40 | fifo | srl | 0 | | b_local_41_U | - | | b_local_41 | fifo | srl | 0 | | b_local_42_U | - | | b_local_42 | fifo | srl | 0 | | b_local_43_U | - | | b_local_43 | fifo | srl | 0 | | b_local_44_U | - | | b_local_44 | fifo | srl | 0 | | b_local_45_U | - | | b_local_45 | fifo | srl | 0 | | b_local_46_U | - | | b_local_46 | fifo | srl | 0 | | b_local_47_U | - | | b_local_47 | fifo | srl | 0 | | b_local_48_U | - | | b_local_48 | fifo | srl | 0 | | b_local_49_U | - | | b_local_49 | fifo | srl | 0 | | b_local_50_U | - | | b_local_50 | fifo | srl | 0 | | b_local_51_U | - | | b_local_51 | fifo | srl | 0 | | b_local_52_U | - | | b_local_52 | fifo | srl | 0 | | b_local_53_U | - | | b_local_53 | fifo | srl | 0 | | b_local_54_U | - | | b_local_54 | fifo | srl | 0 | | b_local_55_U | - | | b_local_55 | fifo | srl | 0 | | b_local_56_U | - | | b_local_56 | fifo | srl | 0 | | b_local_57_U | - | | b_local_57 | fifo | srl | 0 | | b_local_58_U | - | | b_local_58 | fifo | srl | 0 | | b_local_59_U | - | | b_local_59 | fifo | srl | 0 | | b_local_60_U | - | | b_local_60 | fifo | srl | 0 | | b_local_61_U | - | | b_local_61 | fifo | srl | 0 | | b_local_62_U | - | | b_local_62 | fifo | srl | 0 | | b_local_63_U | - | | b_local_63 | fifo | srl | 0 | | c_local_U | - | | c_local | fifo | srl | 0 | | c_local_1_U | - | | c_local_1 | fifo | srl | 0 | | c_local_2_U | - | | c_local_2 | fifo | srl | 0 | | c_local_3_U | - | | c_local_3 | fifo | srl | 0 | | c_local_4_U | - | | c_local_4 | fifo | srl | 0 | | c_local_5_U | - | | c_local_5 | fifo | srl | 0 | | c_local_6_U | - | | c_local_6 | fifo | srl | 0 | | c_local_7_U | - | | c_local_7 | fifo | srl | 0 | | c_local_8_U | - | | c_local_8 | fifo | srl | 0 | | c_local_9_U | - | | c_local_9 | fifo | srl | 0 | | c_local_10_U | - | | c_local_10 | fifo | srl | 0 | | c_local_11_U | - | | c_local_11 | fifo | srl | 0 | | c_local_12_U | - | | c_local_12 | fifo | srl | 0 | | c_local_13_U | - | | c_local_13 | fifo | srl | 0 | | c_local_14_U | - | | c_local_14 | fifo | srl | 0 | | c_local_15_U | - | | c_local_15 | fifo | srl | 0 | | c_local_16_U | - | | c_local_16 | fifo | srl | 0 | | c_local_17_U | - | | c_local_17 | fifo | srl | 0 | | c_local_18_U | - | | c_local_18 | fifo | srl | 0 | | c_local_19_U | - | | c_local_19 | fifo | srl | 0 | | c_local_20_U | - | | c_local_20 | fifo | srl | 0 | | c_local_21_U | - | | c_local_21 | fifo | srl | 0 | | c_local_22_U | - | | c_local_22 | fifo | srl | 0 | | c_local_23_U | - | | c_local_23 | fifo | srl | 0 | | c_local_24_U | - | | c_local_24 | fifo | srl | 0 | | c_local_25_U | - | | c_local_25 | fifo | srl | 0 | | c_local_26_U | - | | c_local_26 | fifo | srl | 0 | | c_local_27_U | - | | c_local_27 | fifo | srl | 0 | | c_local_28_U | - | | c_local_28 | fifo | srl | 0 | | c_local_29_U | - | | c_local_29 | fifo | srl | 0 | | c_local_30_U | - | | c_local_30 | fifo | srl | 0 | | c_local_31_U | - | | c_local_31 | fifo | srl | 0 | | c_local_32_U | - | | c_local_32 | fifo | srl | 0 | | c_local_33_U | - | | c_local_33 | fifo | srl | 0 | | c_local_34_U | - | | c_local_34 | fifo | srl | 0 | | c_local_35_U | - | | c_local_35 | fifo | srl | 0 | | c_local_36_U | - | | c_local_36 | fifo | srl | 0 | | c_local_37_U | - | | c_local_37 | fifo | srl | 0 | | c_local_38_U | - | | c_local_38 | fifo | srl | 0 | | c_local_39_U | - | | c_local_39 | fifo | srl | 0 | | c_local_40_U | - | | c_local_40 | fifo | srl | 0 | | c_local_41_U | - | | c_local_41 | fifo | srl | 0 | | c_local_42_U | - | | c_local_42 | fifo | srl | 0 | | c_local_43_U | - | | c_local_43 | fifo | srl | 0 | | c_local_44_U | - | | c_local_44 | fifo | srl | 0 | | c_local_45_U | - | | c_local_45 | fifo | srl | 0 | | c_local_46_U | - | | c_local_46 | fifo | srl | 0 | | c_local_47_U | - | | c_local_47 | fifo | srl | 0 | | c_local_48_U | - | | c_local_48 | fifo | srl | 0 | | c_local_49_U | - | | c_local_49 | fifo | srl | 0 | | c_local_50_U | - | | c_local_50 | fifo | srl | 0 | | c_local_51_U | - | | c_local_51 | fifo | srl | 0 | | c_local_52_U | - | | c_local_52 | fifo | srl | 0 | | c_local_53_U | - | | c_local_53 | fifo | srl | 0 | | c_local_54_U | - | | c_local_54 | fifo | srl | 0 | | c_local_55_U | - | | c_local_55 | fifo | srl | 0 | | c_local_56_U | - | | c_local_56 | fifo | srl | 0 | | c_local_57_U | - | | c_local_57 | fifo | srl | 0 | | c_local_58_U | - | | c_local_58 | fifo | srl | 0 | | c_local_59_U | - | | c_local_59 | fifo | srl | 0 | | c_local_60_U | - | | c_local_60 | fifo | srl | 0 | | c_local_61_U | - | | c_local_61 | fifo | srl | 0 | | c_local_62_U | - | | c_local_62 | fifo | srl | 0 | | c_local_63_U | - | | c_local_63 | fifo | srl | 0 | | + load_matA | 0 | | | | | | | add_ln8_fu_140_p2 | - | | add_ln8 | add | fabric | 0 | | add_ln13_fu_197_p2 | - | | add_ln13 | add | fabric | 0 | | + load_vecB | 0 | | | | | | | add_ln24_fu_490_p2 | - | | add_ln24 | add | fabric | 0 | | + mat_mult | 192 | | | | | | | + mat_mult_Pipeline_I_loop | 192 | | | | | | | add_ln34_fu_2419_p2 | - | | add_ln34 | add | fabric | 0 | | mul_32s_32s_32_1_1_U70 | 3 | | mul_ln40 | mul | auto | 0 | | mul_32s_32s_32_1_1_U8 | 3 | | mul_ln40_1 | mul | auto | 0 | | mul_32s_32s_32_1_1_U9 | 3 | | mul_ln40_2 | mul | auto | 0 | | mul_32s_32s_32_1_1_U10 | 3 | | mul_ln40_3 | mul | auto | 0 | | mul_32s_32s_32_1_1_U71 | 3 | | mul_ln40_4 | mul | auto | 0 | | mul_32s_32s_32_1_1_U11 | 3 | | mul_ln40_5 | mul | auto | 0 | | mul_32s_32s_32_1_1_U12 | 3 | | mul_ln40_6 | mul | auto | 0 | | mul_32s_32s_32_1_1_U13 | 3 | | mul_ln40_7 | mul | auto | 0 | | mul_32s_32s_32_1_1_U14 | 3 | | mul_ln40_8 | mul | auto | 0 | | mul_32s_32s_32_1_1_U15 | 3 | | mul_ln40_9 | mul | auto | 0 | | mul_32s_32s_32_1_1_U16 | 3 | | mul_ln40_10 | mul | auto | 0 | | mul_32s_32s_32_1_1_U17 | 3 | | mul_ln40_11 | mul | auto | 0 | | mul_32s_32s_32_1_1_U18 | 3 | | mul_ln40_12 | mul | auto | 0 | | mul_32s_32s_32_1_1_U19 | 3 | | mul_ln40_13 | mul | auto | 0 | | mul_32s_32s_32_1_1_U20 | 3 | | mul_ln40_14 | mul | auto | 0 | | mul_32s_32s_32_1_1_U21 | 3 | | mul_ln40_15 | mul | auto | 0 | | mul_32s_32s_32_1_1_U22 | 3 | | mul_ln40_16 | mul | auto | 0 | | mul_32s_32s_32_1_1_U23 | 3 | | mul_ln40_17 | mul | auto | 0 | | mul_32s_32s_32_1_1_U24 | 3 | | mul_ln40_18 | mul | auto | 0 | | mul_32s_32s_32_1_1_U25 | 3 | | mul_ln40_19 | mul | auto | 0 | | mul_32s_32s_32_1_1_U26 | 3 | | mul_ln40_20 | mul | auto | 0 | | mul_32s_32s_32_1_1_U27 | 3 | | mul_ln40_21 | mul | auto | 0 | | mul_32s_32s_32_1_1_U28 | 3 | | mul_ln40_22 | mul | auto | 0 | | mul_32s_32s_32_1_1_U29 | 3 | | mul_ln40_23 | mul | auto | 0 | | mul_32s_32s_32_1_1_U30 | 3 | | mul_ln40_24 | mul | auto | 0 | | mul_32s_32s_32_1_1_U31 | 3 | | mul_ln40_25 | mul | auto | 0 | | mul_32s_32s_32_1_1_U32 | 3 | | mul_ln40_26 | mul | auto | 0 | | mul_32s_32s_32_1_1_U33 | 3 | | mul_ln40_27 | mul | auto | 0 | | mul_32s_32s_32_1_1_U34 | 3 | | mul_ln40_28 | mul | auto | 0 | | mul_32s_32s_32_1_1_U35 | 3 | | mul_ln40_29 | mul | auto | 0 | | mul_32s_32s_32_1_1_U36 | 3 | | mul_ln40_30 | mul | auto | 0 | | mul_32s_32s_32_1_1_U37 | 3 | | mul_ln40_31 | mul | auto | 0 | | mul_32s_32s_32_1_1_U38 | 3 | | mul_ln40_32 | mul | auto | 0 | | mul_32s_32s_32_1_1_U39 | 3 | | mul_ln40_33 | mul | auto | 0 | | mul_32s_32s_32_1_1_U40 | 3 | | mul_ln40_34 | mul | auto | 0 | | mul_32s_32s_32_1_1_U41 | 3 | | mul_ln40_35 | mul | auto | 0 | | mul_32s_32s_32_1_1_U42 | 3 | | mul_ln40_36 | mul | auto | 0 | | mul_32s_32s_32_1_1_U43 | 3 | | mul_ln40_37 | mul | auto | 0 | | mul_32s_32s_32_1_1_U44 | 3 | | mul_ln40_38 | mul | auto | 0 | | mul_32s_32s_32_1_1_U45 | 3 | | mul_ln40_39 | mul | auto | 0 | | mul_32s_32s_32_1_1_U46 | 3 | | mul_ln40_40 | mul | auto | 0 | | mul_32s_32s_32_1_1_U47 | 3 | | mul_ln40_41 | mul | auto | 0 | | mul_32s_32s_32_1_1_U48 | 3 | | mul_ln40_42 | mul | auto | 0 | | mul_32s_32s_32_1_1_U49 | 3 | | mul_ln40_43 | mul | auto | 0 | | mul_32s_32s_32_1_1_U50 | 3 | | mul_ln40_44 | mul | auto | 0 | | mul_32s_32s_32_1_1_U51 | 3 | | mul_ln40_45 | mul | auto | 0 | | mul_32s_32s_32_1_1_U52 | 3 | | mul_ln40_46 | mul | auto | 0 | | mul_32s_32s_32_1_1_U53 | 3 | | mul_ln40_47 | mul | auto | 0 | | mul_32s_32s_32_1_1_U54 | 3 | | mul_ln40_48 | mul | auto | 0 | | mul_32s_32s_32_1_1_U55 | 3 | | mul_ln40_49 | mul | auto | 0 | | mul_32s_32s_32_1_1_U56 | 3 | | mul_ln40_50 | mul | auto | 0 | | mul_32s_32s_32_1_1_U57 | 3 | | mul_ln40_51 | mul | auto | 0 | | mul_32s_32s_32_1_1_U58 | 3 | | mul_ln40_52 | mul | auto | 0 | | mul_32s_32s_32_1_1_U59 | 3 | | mul_ln40_53 | mul | auto | 0 | | mul_32s_32s_32_1_1_U60 | 3 | | mul_ln40_54 | mul | auto | 0 | | mul_32s_32s_32_1_1_U61 | 3 | | mul_ln40_55 | mul | auto | 0 | | mul_32s_32s_32_1_1_U62 | 3 | | mul_ln40_56 | mul | auto | 0 | | mul_32s_32s_32_1_1_U63 | 3 | | mul_ln40_57 | mul | auto | 0 | | mul_32s_32s_32_1_1_U64 | 3 | | mul_ln40_58 | mul | auto | 0 | | mul_32s_32s_32_1_1_U65 | 3 | | mul_ln40_59 | mul | auto | 0 | | mul_32s_32s_32_1_1_U66 | 3 | | mul_ln40_60 | mul | auto | 0 | | mul_32s_32s_32_1_1_U67 | 3 | | mul_ln40_61 | mul | auto | 0 | | mul_32s_32s_32_1_1_U68 | 3 | | mul_ln40_62 | mul | auto | 0 | | mul_32s_32s_32_1_1_U69 | 3 | | mul_ln40_63 | mul | auto | 0 | | add_ln40_1_fu_2431_p2 | - | | add_ln40_1 | add | fabric | 0 | | add_ln40_4_fu_2449_p2 | - | | add_ln40_4 | add | fabric | 0 | | add_ln40_7_fu_2467_p2 | - | | add_ln40_7 | add | fabric | 0 | | add_ln40_8_fu_2473_p2 | - | | add_ln40_8 | add | fabric | 0 | | add_ln40_11_fu_2491_p2 | - | | add_ln40_11 | add | fabric | 0 | | add_ln40_16_fu_2521_p2 | - | | add_ln40_16 | add | fabric | 0 | | add_ln40_19_fu_2539_p2 | - | | add_ln40_19 | add | fabric | 0 | | add_ln40_22_fu_2557_p2 | - | | add_ln40_22 | add | fabric | 0 | | add_ln40_23_fu_2563_p2 | - | | add_ln40_23 | add | fabric | 0 | | add_ln40_26_fu_2581_p2 | - | | add_ln40_26 | add | fabric | 0 | | add_ln40_31_fu_2605_p2 | - | | add_ln40_31 | add | fabric | 0 | | add_ln40_32_fu_2774_p2 | - | | add_ln40_32 | add | fabric | 0 | | add_ln40_35_fu_2617_p2 | - | | add_ln40_35 | add | fabric | 0 | | add_ln40_38_fu_2629_p2 | - | | add_ln40_38 | add | fabric | 0 | | add_ln40_39_fu_2635_p2 | - | | add_ln40_39 | add | fabric | 0 | | add_ln40_42_fu_2653_p2 | - | | add_ln40_42 | add | fabric | 0 | | add_ln40_47_fu_2677_p2 | - | | add_ln40_47 | add | fabric | 0 | | add_ln40_50_fu_2695_p2 | - | | add_ln40_50 | add | fabric | 0 | | add_ln40_53_fu_2713_p2 | - | | add_ln40_53 | add | fabric | 0 | | add_ln40_54_fu_2719_p2 | - | | add_ln40_54 | add | fabric | 0 | | add_ln40_57_fu_2737_p2 | - | | add_ln40_57 | add | fabric | 0 | | + store_result | 0 | | | | | | | add_ln49_fu_642_p2 | - | | add_ln49 | add | fabric | 0 | +------------------------------+-----+--------+-------------+------+--------+---------+ ================================================================ == Bind Storage Report ================================================================ +-----------------+------+------+--------+----------+---------+------+---------+ | Name | BRAM | URAM | Pragma | Variable | Storage | Impl | Latency | +-----------------+------+------+--------+----------+---------+------+---------+ | + matv_mult_opt | 4 | 0 | | | | | | | c_c_U | - | - | | c_c | fifo | srl | 0 | | a_local_U | - | - | | a_local | ram_s2p | auto | 1 | +-----------------+------+------+--------+----------+---------+------+---------+ ================================================================ == Pragma Report ================================================================ * Valid Pragma Syntax +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+ | Type | Options | Location | +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+ | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:11 in load_mata | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:14 in load_mata | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:25 in load_vecb | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:35 in mat_mult | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:39 in mat_mult | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:50 in store_result | | interface | m_axi port=a bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:61 in matv_mult_opt, a | | interface | m_axi port=b bundle=aximm2 max_read_burst_length = 16 max_write_burst_length = 1 | ../src/matv_mult_opt.cpp:62 in matv_mult_opt, b | | interface | m_axi port=c bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:63 in matv_mult_opt, c | | dataflow | | ../src/matv_mult_opt.cpp:65 in matv_mult_opt | | array_partition | variable=a_local type=complete | ../src/matv_mult_opt.cpp:73 in matv_mult_opt, a_local | | array_partition | variable=b_local type=complete | ../src/matv_mult_opt.cpp:74 in matv_mult_opt, b_local | | array_partition | variable=c_local type=complete | ../src/matv_mult_opt.cpp:75 in matv_mult_opt, c_local | +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+