================================================================ == Synthesis Summary Report of 'matv_mult_opt' ================================================================ + General Information: * Date: Sat Dec 2 10:39:21 2023 * Version: 2023.1 (Build 3854077 on May 4 2023) * Project: proj * Solution: solution (Vivado IP Flow Target) * Product family: virtexuplus * Target device: xcu250-figd2104-2L-e + Performance & Resource Estimates: PS: '+' for module; 'o' for loop; '*' for dataflow +---------------------------------------------+--------+-------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+------------+-----+ | Modules | Issue | | Latency | Latency | Iteration| | Trip | | | | | | | | & Loops | Type | Slack | (cycles)| (ns) | Latency | Interval| Count| Pipelined| BRAM | DSP | FF | LUT | URAM| +---------------------------------------------+--------+-------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+------------+-----+ |+ matv_mult_opt | Timing| -0.45| 4283| 4.283e+04| -| 4284| -| no| 4 (~0%)| 192 (1%)| 139378 (4%)| 47097 (2%)| -| | + matv_mult_opt_Pipeline_I_load_a_J_load_a | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 65 (~0%)| 167 (~0%)| -| | o I_load_a_J_load_a | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_load_b | -| 0.00| 66| 660.000| -| 66| -| no| -| -| 2064 (~0%)| 78 (~0%)| -| | o I_load_b | -| 7.30| 64| 640.000| 2| 1| 64| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_loop | -| 0.31| 66| 660.000| -| 66| -| no| -| 192 (1%)| 2224 (~0%)| 20982 (1%)| -| | o I_loop | -| 7.30| 64| 640.000| 2| 1| 64| yes| -| -| -| -| -| | + matv_mult_opt_Pipeline_I_store_c | -| 0.00| 66| 660.000| -| 66| -| no| -| -| 42 (~0%)| 351 (~0%)| -| | o I_store_c | -| 7.30| 64| 640.000| 2| 1| 64| yes| -| -| -| -| -| +---------------------------------------------+--------+-------+---------+-----------+----------+---------+------+----------+---------+----------+-------------+------------+-----+ ================================================================ == HW Interfaces ================================================================ * M_AXI +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | Interface | Data Width | Address Width | Latency | Offset | Register | Max Widen | Max Read | Max Write | Num Read | Num Write | Resource Estimate | | | (SW->HW) | | | | | Bitwidth | Burst Length | Burst Length | Outstanding | Outstanding | | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ | m_axi_aximm1 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 16 | 16 | 16 | BRAM=2 | | m_axi_aximm2 | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 1 | 16 | 16 | BRAM=2 | +--------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+ * S_AXILITE Interfaces +---------------+------------+---------------+--------+----------+ | Interface | Data Width | Address Width | Offset | Register | +---------------+------------+---------------+--------+----------+ | s_axi_control | 32 | 6 | 16 | 0 | +---------------+------------+---------------+--------+----------+ * S_AXILITE Registers +---------------+----------+--------+-------+--------+------------------+ | Interface | Register | Offset | Width | Access | Description | +---------------+----------+--------+-------+--------+------------------+ | s_axi_control | c_1 | 0x10 | 32 | W | Data signal of c | | s_axi_control | c_2 | 0x14 | 32 | W | Data signal of c | | s_axi_control | a_1 | 0x1c | 32 | W | Data signal of a | | s_axi_control | a_2 | 0x20 | 32 | W | Data signal of a | | s_axi_control | b_1 | 0x28 | 32 | W | Data signal of b | | s_axi_control | b_2 | 0x2c | 32 | W | Data signal of b | +---------------+----------+--------+-------+--------+------------------+ * TOP LEVEL CONTROL +-----------+------------+-----------------------------------+ | Interface | Type | Ports | +-----------+------------+-----------------------------------+ | ap_clk | clock | ap_clk | | ap_rst_n | reset | ap_rst_n | | ap_ctrl | ap_ctrl_hs | ap_done ap_idle ap_ready ap_start | +-----------+------------+-----------------------------------+ ================================================================ == SW I/O Information ================================================================ * Top Function Arguments +----------+-----------+-------------+ | Argument | Direction | Datatype | +----------+-----------+-------------+ | c | inout | int* | | a | inout | int const * | | b | in | int const * | +----------+-----------+-------------+ * SW-to-HW Mapping +----------+---------------+-----------+----------+-------------------------------+ | Argument | HW Interface | HW Type | HW Usage | HW Info | +----------+---------------+-----------+----------+-------------------------------+ | c | m_axi_aximm1 | interface | | | | c | s_axi_control | register | offset | name=c_1 offset=0x10 range=32 | | c | s_axi_control | register | offset | name=c_2 offset=0x14 range=32 | | a | m_axi_aximm1 | interface | | | | a | s_axi_control | register | offset | name=a_1 offset=0x1c range=32 | | a | s_axi_control | register | offset | name=a_2 offset=0x20 range=32 | | b | m_axi_aximm2 | interface | | | | b | s_axi_control | register | offset | name=b_1 offset=0x28 range=32 | | b | s_axi_control | register | offset | name=b_2 offset=0x2c range=32 | +----------+---------------+-----------+----------+-------------------------------+ ================================================================ == M_AXI Burst Information ================================================================ Note: All burst requests might be further partitioned into multiple requests during RTL generation based on max_read_burst_length or max_write_burst_length settings. * Inferred Burst Summary +--------------+-----------+--------+-------+-----------+-------------------------------+ | HW Interface | Direction | Length | Width | Loop | Loop Location | +--------------+-----------+--------+-------+-----------+-------------------------------+ | m_axi_aximm1 | read | 4096 | 32 | I_load_a | ../src/matv_mult_opt.cpp:27:9 | | m_axi_aximm1 | write | 64 | 32 | I_store_c | ../src/matv_mult_opt.cpp:88:9 | | m_axi_aximm2 | read | 64 | 32 | I_load_b | ../src/matv_mult_opt.cpp:40:9 | +--------------+-----------+--------+-------+-----------+-------------------------------+ * All M_AXI Variable Accesses +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | HW Interface | Variable | Access Location | Direction | Burst Status | Length | Loop | Loop Location | Resolution | Problem | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:34:18 | read | Widen Fail | | J_load_a | ../src/matv_mult_opt.cpp:32:13 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | a | ../src/matv_mult_opt.cpp:34:18 | read | Inferred | 4096 | I_load_a | ../src/matv_mult_opt.cpp:27:9 | | | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:90:11 | write | Widen Fail | | I_store_c | ../src/matv_mult_opt.cpp:88:9 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm1 | c | ../src/matv_mult_opt.cpp:90:11 | write | Inferred | 64 | I_store_c | ../src/matv_mult_opt.cpp:88:9 | | | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:42:15 | read | Widen Fail | | I_load_b | ../src/matv_mult_opt.cpp:40:9 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 | | m_axi_aximm2 | b | ../src/matv_mult_opt.cpp:42:15 | read | Inferred | 64 | I_load_b | ../src/matv_mult_opt.cpp:40:9 | | | +--------------+----------+--------------------------------+-----------+--------------+--------+-----------+--------------------------------+------------+-------------------------------------------------------------------------------------------------------+ * Resolution URL: www.xilinx.com/cgi-bin/docs/rdoc?v=2023.1;t=hls+guidance;d=XXX-YYY.html (replace XXX-YYY with column value) ================================================================ == Bind Op Report ================================================================ +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ | Name | DSP | Pragma | Variable | Op | Impl | Latency | +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ | + matv_mult_opt | 192 | | | | | | | + matv_mult_opt_Pipeline_I_load_a_J_load_a | 0 | | | | | | | add_ln27_fu_1193_p2 | - | | add_ln27 | add | fabric | 0 | | add_ln27_1_fu_1230_p2 | - | | add_ln27_1 | add | fabric | 0 | | add_ln32_fu_1316_p2 | - | | add_ln32 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_load_b | 0 | | | | | | | add_ln40_fu_1045_p2 | - | | add_ln40 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_loop | 192 | | | | | | | add_ln49_fu_34606_p2 | - | | add_ln49 | add | fabric | 0 | | mul_32s_32s_32_1_1_U133 | 3 | | mul_ln55 | mul | auto | 0 | | mul_32s_32s_32_1_1_U134 | 3 | | mul_ln55_1 | mul | auto | 0 | | mul_32s_32s_32_1_1_U135 | 3 | | mul_ln55_2 | mul | auto | 0 | | mul_32s_32s_32_1_1_U136 | 3 | | mul_ln55_3 | mul | auto | 0 | | mul_32s_32s_32_1_1_U137 | 3 | | mul_ln55_4 | mul | auto | 0 | | mul_32s_32s_32_1_1_U138 | 3 | | mul_ln55_5 | mul | auto | 0 | | mul_32s_32s_32_1_1_U139 | 3 | | mul_ln55_6 | mul | auto | 0 | | mul_32s_32s_32_1_1_U140 | 3 | | mul_ln55_7 | mul | auto | 0 | | mul_32s_32s_32_1_1_U141 | 3 | | mul_ln55_8 | mul | auto | 0 | | mul_32s_32s_32_1_1_U142 | 3 | | mul_ln55_9 | mul | auto | 0 | | mul_32s_32s_32_1_1_U143 | 3 | | mul_ln55_10 | mul | auto | 0 | | mul_32s_32s_32_1_1_U144 | 3 | | mul_ln55_11 | mul | auto | 0 | | mul_32s_32s_32_1_1_U145 | 3 | | mul_ln55_12 | mul | auto | 0 | | mul_32s_32s_32_1_1_U146 | 3 | | mul_ln55_13 | mul | auto | 0 | | mul_32s_32s_32_1_1_U147 | 3 | | mul_ln55_14 | mul | auto | 0 | | mul_32s_32s_32_1_1_U148 | 3 | | mul_ln55_15 | mul | auto | 0 | | mul_32s_32s_32_1_1_U149 | 3 | | mul_ln55_16 | mul | auto | 0 | | mul_32s_32s_32_1_1_U150 | 3 | | mul_ln55_17 | mul | auto | 0 | | mul_32s_32s_32_1_1_U151 | 3 | | mul_ln55_18 | mul | auto | 0 | | mul_32s_32s_32_1_1_U152 | 3 | | mul_ln55_19 | mul | auto | 0 | | mul_32s_32s_32_1_1_U153 | 3 | | mul_ln55_20 | mul | auto | 0 | | mul_32s_32s_32_1_1_U154 | 3 | | mul_ln55_21 | mul | auto | 0 | | mul_32s_32s_32_1_1_U155 | 3 | | mul_ln55_22 | mul | auto | 0 | | mul_32s_32s_32_1_1_U156 | 3 | | mul_ln55_23 | mul | auto | 0 | | mul_32s_32s_32_1_1_U157 | 3 | | mul_ln55_24 | mul | auto | 0 | | mul_32s_32s_32_1_1_U158 | 3 | | mul_ln55_25 | mul | auto | 0 | | mul_32s_32s_32_1_1_U159 | 3 | | mul_ln55_26 | mul | auto | 0 | | mul_32s_32s_32_1_1_U160 | 3 | | mul_ln55_27 | mul | auto | 0 | | mul_32s_32s_32_1_1_U161 | 3 | | mul_ln55_28 | mul | auto | 0 | | mul_32s_32s_32_1_1_U162 | 3 | | mul_ln55_29 | mul | auto | 0 | | mul_32s_32s_32_1_1_U163 | 3 | | mul_ln55_30 | mul | auto | 0 | | mul_32s_32s_32_1_1_U164 | 3 | | mul_ln55_31 | mul | auto | 0 | | mul_32s_32s_32_1_1_U165 | 3 | | mul_ln55_32 | mul | auto | 0 | | mul_32s_32s_32_1_1_U166 | 3 | | mul_ln55_33 | mul | auto | 0 | | mul_32s_32s_32_1_1_U167 | 3 | | mul_ln55_34 | mul | auto | 0 | | mul_32s_32s_32_1_1_U168 | 3 | | mul_ln55_35 | mul | auto | 0 | | mul_32s_32s_32_1_1_U169 | 3 | | mul_ln55_36 | mul | auto | 0 | | mul_32s_32s_32_1_1_U170 | 3 | | mul_ln55_37 | mul | auto | 0 | | mul_32s_32s_32_1_1_U171 | 3 | | mul_ln55_38 | mul | auto | 0 | | mul_32s_32s_32_1_1_U172 | 3 | | mul_ln55_39 | mul | auto | 0 | | mul_32s_32s_32_1_1_U173 | 3 | | mul_ln55_40 | mul | auto | 0 | | mul_32s_32s_32_1_1_U174 | 3 | | mul_ln55_41 | mul | auto | 0 | | mul_32s_32s_32_1_1_U175 | 3 | | mul_ln55_42 | mul | auto | 0 | | mul_32s_32s_32_1_1_U176 | 3 | | mul_ln55_43 | mul | auto | 0 | | mul_32s_32s_32_1_1_U177 | 3 | | mul_ln55_44 | mul | auto | 0 | | mul_32s_32s_32_1_1_U178 | 3 | | mul_ln55_45 | mul | auto | 0 | | mul_32s_32s_32_1_1_U179 | 3 | | mul_ln55_46 | mul | auto | 0 | | mul_32s_32s_32_1_1_U180 | 3 | | mul_ln55_47 | mul | auto | 0 | | mul_32s_32s_32_1_1_U181 | 3 | | mul_ln55_48 | mul | auto | 0 | | mul_32s_32s_32_1_1_U182 | 3 | | mul_ln55_49 | mul | auto | 0 | | mul_32s_32s_32_1_1_U183 | 3 | | mul_ln55_50 | mul | auto | 0 | | mul_32s_32s_32_1_1_U184 | 3 | | mul_ln55_51 | mul | auto | 0 | | mul_32s_32s_32_1_1_U185 | 3 | | mul_ln55_52 | mul | auto | 0 | | mul_32s_32s_32_1_1_U186 | 3 | | mul_ln55_53 | mul | auto | 0 | | mul_32s_32s_32_1_1_U187 | 3 | | mul_ln55_54 | mul | auto | 0 | | mul_32s_32s_32_1_1_U188 | 3 | | mul_ln55_55 | mul | auto | 0 | | mul_32s_32s_32_1_1_U189 | 3 | | mul_ln55_56 | mul | auto | 0 | | mul_32s_32s_32_1_1_U190 | 3 | | mul_ln55_57 | mul | auto | 0 | | mul_32s_32s_32_1_1_U191 | 3 | | mul_ln55_58 | mul | auto | 0 | | mul_32s_32s_32_1_1_U192 | 3 | | mul_ln55_59 | mul | auto | 0 | | mul_32s_32s_32_1_1_U193 | 3 | | mul_ln55_60 | mul | auto | 0 | | mul_32s_32s_32_1_1_U194 | 3 | | mul_ln55_61 | mul | auto | 0 | | mul_32s_32s_32_1_1_U195 | 3 | | mul_ln55_62 | mul | auto | 0 | | mul_32s_32s_32_1_1_U196 | 3 | | mul_ln55_63 | mul | auto | 0 | | add_ln55_1_fu_43262_p2 | - | | add_ln55_1 | add | fabric | 0 | | add_ln55_4_fu_43280_p2 | - | | add_ln55_4 | add | fabric | 0 | | add_ln55_7_fu_43298_p2 | - | | add_ln55_7 | add | fabric | 0 | | add_ln55_8_fu_43304_p2 | - | | add_ln55_8 | add | fabric | 0 | | add_ln55_11_fu_43322_p2 | - | | add_ln55_11 | add | fabric | 0 | | add_ln55_16_fu_43352_p2 | - | | add_ln55_16 | add | fabric | 0 | | add_ln55_19_fu_43370_p2 | - | | add_ln55_19 | add | fabric | 0 | | add_ln55_22_fu_43388_p2 | - | | add_ln55_22 | add | fabric | 0 | | add_ln55_23_fu_43394_p2 | - | | add_ln55_23 | add | fabric | 0 | | add_ln55_26_fu_43412_p2 | - | | add_ln55_26 | add | fabric | 0 | | add_ln55_31_fu_43436_p2 | - | | add_ln55_31 | add | fabric | 0 | | add_ln55_32_fu_43442_p2 | - | | add_ln55_32 | add | fabric | 0 | | add_ln55_35_fu_43460_p2 | - | | add_ln55_35 | add | fabric | 0 | | add_ln55_38_fu_43478_p2 | - | | add_ln55_38 | add | fabric | 0 | | add_ln55_39_fu_43484_p2 | - | | add_ln55_39 | add | fabric | 0 | | add_ln55_42_fu_43502_p2 | - | | add_ln55_42 | add | fabric | 0 | | add_ln55_47_fu_43526_p2 | - | | add_ln55_47 | add | fabric | 0 | | add_ln55_50_fu_43544_p2 | - | | add_ln55_50 | add | fabric | 0 | | add_ln55_53_fu_43562_p2 | - | | add_ln55_53 | add | fabric | 0 | | add_ln55_54_fu_43568_p2 | - | | add_ln55_54 | add | fabric | 0 | | add_ln55_57_fu_43586_p2 | - | | add_ln55_57 | add | fabric | 0 | | + matv_mult_opt_Pipeline_I_store_c | 0 | | | | | | | add_ln88_fu_606_p2 | - | | add_ln88 | add | fabric | 0 | +---------------------------------------------+-----+--------+-------------+-----+--------+---------+ ================================================================ == Bind Storage Report ================================================================ +-----------------+------+------+--------+------------+---------+------+---------+ | Name | BRAM | URAM | Pragma | Variable | Storage | Impl | Latency | +-----------------+------+------+--------+------------+---------+------+---------+ | + matv_mult_opt | 4 | 0 | | | | | | | a_local_U | - | - | | a_local | ram_s2p | auto | 1 | | a_local_1_U | - | - | | a_local_1 | ram_s2p | auto | 1 | | a_local_2_U | - | - | | a_local_2 | ram_s2p | auto | 1 | | a_local_3_U | - | - | | a_local_3 | ram_s2p | auto | 1 | | a_local_4_U | - | - | | a_local_4 | ram_s2p | auto | 1 | | a_local_5_U | - | - | | a_local_5 | ram_s2p | auto | 1 | | a_local_6_U | - | - | | a_local_6 | ram_s2p | auto | 1 | | a_local_7_U | - | - | | a_local_7 | ram_s2p | auto | 1 | | a_local_8_U | - | - | | a_local_8 | ram_s2p | auto | 1 | | a_local_9_U | - | - | | a_local_9 | ram_s2p | auto | 1 | | a_local_10_U | - | - | | a_local_10 | ram_s2p | auto | 1 | | a_local_11_U | - | - | | a_local_11 | ram_s2p | auto | 1 | | a_local_12_U | - | - | | a_local_12 | ram_s2p | auto | 1 | | a_local_13_U | - | - | | a_local_13 | ram_s2p | auto | 1 | | a_local_14_U | - | - | | a_local_14 | ram_s2p | auto | 1 | | a_local_15_U | - | - | | a_local_15 | ram_s2p | auto | 1 | | a_local_16_U | - | - | | a_local_16 | ram_s2p | auto | 1 | | a_local_17_U | - | - | | a_local_17 | ram_s2p | auto | 1 | | a_local_18_U | - | - | | a_local_18 | ram_s2p | auto | 1 | | a_local_19_U | - | - | | a_local_19 | ram_s2p | auto | 1 | | a_local_20_U | - | - | | a_local_20 | ram_s2p | auto | 1 | | a_local_21_U | - | - | | a_local_21 | ram_s2p | auto | 1 | | a_local_22_U | - | - | | a_local_22 | ram_s2p | auto | 1 | | a_local_23_U | - | - | | a_local_23 | ram_s2p | auto | 1 | | a_local_24_U | - | - | | a_local_24 | ram_s2p | auto | 1 | | a_local_25_U | - | - | | a_local_25 | ram_s2p | auto | 1 | | a_local_26_U | - | - | | a_local_26 | ram_s2p | auto | 1 | | a_local_27_U | - | - | | a_local_27 | ram_s2p | auto | 1 | | a_local_28_U | - | - | | a_local_28 | ram_s2p | auto | 1 | | a_local_29_U | - | - | | a_local_29 | ram_s2p | auto | 1 | | a_local_30_U | - | - | | a_local_30 | ram_s2p | auto | 1 | | a_local_31_U | - | - | | a_local_31 | ram_s2p | auto | 1 | | a_local_32_U | - | - | | a_local_32 | ram_s2p | auto | 1 | | a_local_33_U | - | - | | a_local_33 | ram_s2p | auto | 1 | | a_local_34_U | - | - | | a_local_34 | ram_s2p | auto | 1 | | a_local_35_U | - | - | | a_local_35 | ram_s2p | auto | 1 | | a_local_36_U | - | - | | a_local_36 | ram_s2p | auto | 1 | | a_local_37_U | - | - | | a_local_37 | ram_s2p | auto | 1 | | a_local_38_U | - | - | | a_local_38 | ram_s2p | auto | 1 | | a_local_39_U | - | - | | a_local_39 | ram_s2p | auto | 1 | | a_local_40_U | - | - | | a_local_40 | ram_s2p | auto | 1 | | a_local_41_U | - | - | | a_local_41 | ram_s2p | auto | 1 | | a_local_42_U | - | - | | a_local_42 | ram_s2p | auto | 1 | | a_local_43_U | - | - | | a_local_43 | ram_s2p | auto | 1 | | a_local_44_U | - | - | | a_local_44 | ram_s2p | auto | 1 | | a_local_45_U | - | - | | a_local_45 | ram_s2p | auto | 1 | | a_local_46_U | - | - | | a_local_46 | ram_s2p | auto | 1 | | a_local_47_U | - | - | | a_local_47 | ram_s2p | auto | 1 | | a_local_48_U | - | - | | a_local_48 | ram_s2p | auto | 1 | | a_local_49_U | - | - | | a_local_49 | ram_s2p | auto | 1 | | a_local_50_U | - | - | | a_local_50 | ram_s2p | auto | 1 | | a_local_51_U | - | - | | a_local_51 | ram_s2p | auto | 1 | | a_local_52_U | - | - | | a_local_52 | ram_s2p | auto | 1 | | a_local_53_U | - | - | | a_local_53 | ram_s2p | auto | 1 | | a_local_54_U | - | - | | a_local_54 | ram_s2p | auto | 1 | | a_local_55_U | - | - | | a_local_55 | ram_s2p | auto | 1 | | a_local_56_U | - | - | | a_local_56 | ram_s2p | auto | 1 | | a_local_57_U | - | - | | a_local_57 | ram_s2p | auto | 1 | | a_local_58_U | - | - | | a_local_58 | ram_s2p | auto | 1 | | a_local_59_U | - | - | | a_local_59 | ram_s2p | auto | 1 | | a_local_60_U | - | - | | a_local_60 | ram_s2p | auto | 1 | | a_local_61_U | - | - | | a_local_61 | ram_s2p | auto | 1 | | a_local_62_U | - | - | | a_local_62 | ram_s2p | auto | 1 | | a_local_63_U | - | - | | a_local_63 | ram_s2p | auto | 1 | +-----------------+------+------+--------+------------+---------+------+---------+ ================================================================ == Pragma Report ================================================================ * Valid Pragma Syntax +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+ | Type | Options | Location | +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+ | interface | m_axi port=a bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:10 in matv_mult_opt, a | | interface | m_axi port=b bundle=aximm2 max_read_burst_length = 16 max_write_burst_length = 1 | ../src/matv_mult_opt.cpp:11 in matv_mult_opt, b | | interface | m_axi port=c bundle=aximm1 max_read_burst_length = 16 max_write_burst_length = 16 | ../src/matv_mult_opt.cpp:12 in matv_mult_opt, c | | array_partition | variable=a_local type=complete | ../src/matv_mult_opt.cpp:21 in matv_mult_opt, a_local | | array_partition | variable=b_local type=complete | ../src/matv_mult_opt.cpp:22 in matv_mult_opt, b_local | | array_partition | variable=c_local type=complete | ../src/matv_mult_opt.cpp:23 in matv_mult_opt, c_local | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:30 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:33 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:41 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:50 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:54 in matv_mult_opt | | loop_tripcount | max=64 | ../src/matv_mult_opt.cpp:89 in matv_mult_opt | +-----------------+-----------------------------------------------------------------------------------+-------------------------------------------------------+